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Interface

Summary

The Interface is

Coding Guidelines

Coding Guidelines

  • Use one SystemVerilog interface instance per DUT interface

Code Example

The interface construct, enclosed between the keywords interface...endinterface, encapsulates the communication between design blocks, and between design and verification blocks, allowing a smooth migration from abstract system-level design through successive refinement down to lower level register-transfer and structural views of the design. By encapsulating the communication between blocks, the interface construct also facilitates design reuse.

interface.sv
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`ifndef GPIO_UVC_IF_SV
`define GPIO_UVC_IF_SV
interface gpio_uvc_if (
    input logic clk
);
  import gpio_uvc_pkg::*;
  gpio_uvc_data_t gpio_pin;
  gpio_uvc_data_t gpio_pin_passive;
  clocking cb_drv @(posedge clk);
    default output #1ns;
    output gpio_pin;
  endclocking : cb_drv
  clocking cb_mon @(posedge clk);
    default input #1ns;
    input gpio_pin;
    input gpio_pin_passive;
  endclocking : cb_mon
endinterface : gpio_uvc_if
`endif // GPIO_UVC_IF_SV

Reference Material

IEEE

SystemVerilog LRM - 3.5 Interfaces