Register Model

Summary

The UVM Sequence Item is the base class for user-defined transact

Coding Guidelines

Tip

• Use conditional compilation guards to avoid compiling the same include file more than once.
• Create user-defined transaction classes by extending the class uvm_sequence_item.
• Do not use field macros. (This comes at a heavy cost in terms of performance)
• Use the rand qualifier in front of any class member variables that might need to be randomized, now or in the future.
• After any member variables, define a constructor that includes a single string name argument with a default value of the empty string, a call to super.new, and is otherwise empty.

Reference Material

Accellera

• UVM 1.2 Class Reference - Global Declarations for the Register Layer
• UVM 1.2 Class Reference uvm_reg_block
  • UVM 1.2 Class Reference uvm_reg
    • UVM 1.2 Class Reference uvm_reg_field
  • UVM 1.2 Class Reference uvm_mem
• UVM 1.2 Class Reference Index

Verification Methodology Cookbooks

• UVM Cookbook pdf
• Register Package
• Register Model and Structure

Source Code

• Source code uvm_reg_model.svh

• Source code uvm_reg_block.svh

  • Source code uvm_reg.svh
    • Source code uvm_reg_field.svh
  • Source code uvm_mem.svh

• Sourece code uvm_reg_sequence.svh

Tools

• PeakRDL Github Repository
• PeakRDL-uvm GitHub Repository