UVM Coding Guidelines¶

This page collects recommended best practices and style references for writing clean, maintainable, and scalable UVM‑based verification environments.

Following these guidelines helps:

• Improve readability and consistency across the codebase
• Reduce onboarding time for new contributors
• Simplify debugging, reuse, and long‑term maintenance
• Enable smoother integration with third‑party IPs and shared UVCs

General UVM Guidelines¶

These references focus on practical rules and conventions that make everyday UVM development easier and less error‑prone:

• Easier UVM Coding Guidelines (Doulos): A concise, experience‑driven set of recommendations covering structure, naming, phasing, and common pitfalls.
• Verification Academy - UVM Coding Guidelines: Guidelines and best practices from the Verification Academy’s UVM community resources.

Style Guides¶

To ensure consistency at the SystemVerilog level, we strongly recommend adhering to established open‑source style guides:

• lowRISC Verilog Coding Style Guide: General Verilog/SystemVerilog rules covering formatting, naming, and coding conventions.
• lowRISC SystemVerilog Coding Style Guide for Design Verification: Verification‑focused guidelines, including classes, interfaces, assertions, and testbench structure.

Recommendation¶

We encourage all contributors to follow these guidelines consistently across tests, sequences, UVCs, and shared libraries.

Adhering to common rules not only improves code quality, but also enables:

• Easier reviews and collaboration
• Faster root‑cause analysis during regressions
• More reliable reuse across projects and institutes

When in doubt, prioritize clarity and consistency over cleverness.