Resource guide¶

This page collects recommended books, standards, courses, and tools for digital design, verification, and formal methods.

Whether you are getting started or refining an existing workflow, these resources are meant to serve as a curated entry point into widely used methodologies, references, and open‑source ecosystems in the hardware design and verification community.

Books¶

Design¶

• D. M. Harris, Digital design and computer architecture, 2^nd ed. Morgan Kaufmann, 2013.
• S. L. Harris, D. M. Harris, Digital design and computer architecture, ARM® edition. Morgan Kaufmann, 2016.
• S. L. Harris, D. M. Harris, Digital design and computer architecture, RISC-V edition. Morgan Kaufmann, 2022.
• P. P. Chu, FPGA prototyping by systemverilog examples: Xilinx MicroBlaze MCS SoC edition. Wiley, 2018.
• S. Sutherland, S. Davidmann, P. Flake, SystemVerilog for design, 2^nd ed. Springer, 2006.
• A. P. Malvino, J. A. Brown, Digital computer electronics, 3^rd ed. Glencoe, 1993.

Verification¶

• C. Spear, G. J. Tumbush, SystemVerilog for verification, 3^rd ed. Springer, 2012.
• J. Bergeron, Writing testbenches using System Verilog. Springer, 2006.

Formal Verification¶

• E. Seligman, E. T. Schubert, M. V. A. K. Kumar, Formal verification: an essential toolkit for modern VLSI design, 2^nd ed. Elsevier, 2023.

SystemVerilog Assertions (SVA)¶

• A. B. Mehta, System Verilog Assertions and Functional Coverage, 3^rd ed. Springer, 2020.
• E. Cerny, S. Dudani, J. Havlicek, D. Korchemny, SVA: The Power of Assertions in SystemVerilog, 2^nd ed. 2015. Springer, 2015.

Language Reference Manuals (LRM)¶

• IEEE 1364-2005 - Verilog Hardware Description Language
• IEEE 1800-2017 - SystemVerilog Unified Hardware Design, Specification, and Verification Language
• IEEE 1800-2023 - SystemVerilog Unified Hardware Design, Specification, and Verification Language

Courses¶

University¶

• Advanced Electronics Laboratory (University of Torino)

Cadence¶

• Verilog Language and Application Training
• SystemVerilog for Design and Verification Training

Synopsys¶

• Language: System Verilog for RTL Design
• Language: SystemVerilog Testbench

Websites & Communities¶

• VLSI Verify
• Paradigm Works
• Verilab
• ZipCPU
• CHIPS Alliance
• The FOSSi Foundation
• Symbiotic EDA
• DVCon
• SystemVerilog.io
• Circuit Cove

Practice Platforms¶

• HDLBits
• RTLHub
• ChipDev
• Logicode

Tools¶

The following tools are widely used in open‑source and industrial workflows for simulation, linting, synthesis, and formal verification. Whenever possible, both the official website and the source repository are provided.

• Verilator - Fast, cycle‑accurate SystemVerilog simulator, widely used for RTL simulation and CI workflows.
  • Official website
  • GitHub repository
• Verible - SystemVerilog developer tools, including formatting, linting, and parsing utilities.
  • Official website
  • GitHub repository
• YosysHQ - Open‑source synthesis framework and hardware tooling ecosystem.
  • Official website
  • OSS CAD Suite
• SymbiYosys - Formal verification frontend for Yosys
  • GitHub repository
  • Documentation

Documentation & Diagrams¶

• Wavedrom - Timing and waveform diagrams
• Inkscape - Vector grephics and diagrams