Constants¶
Constants are named data objects whose value cannot change after they are defined. SystemVerilog provides both elaboration-time constants and run-time constants.
| Keyword | Scope | Overridable | Typical Usage |
|---|---|---|---|
parameter |
Module / Interface / Class | Yes | Configurable design parameters |
localparam |
Module / Interface / Class | No | Internal constants, derived values |
parameter¶
- Value can be overridden at instantiation
- Commonly used for design configuration
- Participates in generate constructs
Example:
localparam¶
- Value cannot be overridden
- Used to protect internal constants
- Often derived from other parameters
Example:
const¶
Run-time constants are evaluated during simulation, but once assigned, their value cannot be modified.
- Enforces read-only semantics
- Value is set at declaration or construction
- Common in testbenches and classes
Example:
Summary¶
| Feature | parameter |
localparam |
const |
|---|---|---|---|
| Time of evaluation | Elaboration | Elaboration | Run-time |
| Can be overridden | Yes | No | No |
| Can change after initialization | No | No | No |
| Typical domain | RTL / TB | RTL / TB | Mostly TB |
Tips
- Use
parameterfor externally configurable values, localparamfor internal derived constants- and
constto enforce read-only behavior in run-time objects and classes.
Reference Material¶
LRM